The present invention relates to semiconductor design technologies; and, more particularly, to a bleeder circuit for use in the semiconductor memory device.
In recent semiconductor memory devices, a large memory capacity and a high operation speed are rising as the biggest issue. In addition to these requirements, development for low power semiconductor memory device is required to ensure a reliable operation under low power environments. Especially, it is a recent development trend that memories mounted on portable systems such as a portable phone for mobile communications, a notebook computer and the like should be made to consume a minimum power.
One of these efforts is a technique of minimizing current consumption in a core region of memory. The core region consisting of memory cells, bit lines and word lines, is designed according to the strict design rule. Thus, the memory cells are very small in size and also use a low power.
In particular, the precharge of a bit line is one of important techniques related to a speed in an access to cell data. That is, the precharge of the bit line is a technique that precharges the bit line to a certain voltage level in advance before the data access to rapidly do so.
Under the environment, the memory cell has a mesh type in which a plurality of word lines and a plurality of bit lines intersect each other. In this structure, gate residue occurs due to any problem in the manufacturing process of the word line and bit line, which in turn gives rise to a bridge phenomenon.
This bridge causes a short circuit of the word line and bit line.
FIG. 1 is a circuit diagram showing a short circuit of a word line and a bit line.
Referring to FIG. 1, it can be seen that the short circuit occurs due to a bridge phenomenon between the word line and the bit line.
This situation causes a leakage phenomenon (leakage path) which passes a precharge voltage VBLP that is a voltage for precharging the bit line in a standby state through the short circuit and then gets to the ground of a word line driver 103.
This defect in the process increases the power consumption of the semiconductor memory device, thereby reducing power efficiency and deteriorating the performance of products.
In order to solve such a defect in the process, a bleeder circuit has been proposed.
FIG. 2 is a circuit diagram illustrating a conventional bleeder circuit.
Referring to FIG. 2, a bleeder circuit 202 is a bleeder transistor which is arranged in a sub hole area where a word line array and a bit line sense amplifier array intersect each other.
At this time, a booster voltage VPP is always biased to the gate of the bleeder transistor to supply a bit line precharge voltage VBLP to a bit line precharge section 201. And, the bleeder transistor is an NMOS transistor N3 with a large resistance by its long gate.
That is, the bleeder circuit 202 connects the bit line precharge voltage VBLP to the bit line precharge section 201 through the bleeder transistor N3, rather than directly connecting thereto, thereby inducing a reduction in current by an increase in resistance.
Further, a bleed voltage VBLEED created by the bleeder circuit 202 is used as a precharge voltage for precharging a bit line in both an active operation (active mode) and a standby operation (standby mode) of the semiconductor memory device.
However, in case of precharging the bit line with the bleed voltage VBLEED created by drop of the bit line precharge voltage VBLP by a certain voltage, precharge characteristic of the bit line is degraded due to reduction in drivability.
This phenomenon happens frequently, especially in the active operation of the semiconductor memory device, and sensing capability of the bit line sense amplifier is also lowered by degradation of precharge characteristic of the bit line.